This survey compares our scripted KiCad/TOML/Rust/PyTorch flow against commercial PCB tools, open-source PCB routing, and IC physical-design research. The useful lesson is not that we should clone any one tool. It is that mature flows split placement and routing into clearer stages, keep constraints active everywhere, and benchmark post-route outcomes instead of trusting a single objective score.
Altium is not trying to make a black-box autorouter the designer blindly trusts. Its strongest routing story is auto-interactive: the user selects nets, layers, and intent, while the router handles local geometry, obstacle avoidance, differential pair rules, and post-route glossing.
Allegro X is a high-end enterprise PCB platform. Public details are less algorithmic than open tools, but the architecture is clear: constraints, collaboration, advanced routing, real-time checks, package/PCB awareness, and now AI-assisted automation are treated as one system.
Xpedition is positioned as an enterprise PCB environment where routing is not isolated. It is tied to constraints, design reuse, MCAD/ECAD collaboration, verification, supply-chain data, and increasingly AI-assisted workflow support.
This is the closest open-source PCB reference point. KiCad does not rely on a built-in black-box autorouter; its production strength is interactive push-and-shove. Freerouting fills the automatic-routing role through Specctra DSN/SES exchange.
OpenROAD is not a PCB tool, but its architecture is highly relevant. It separates placement, global routing, and detailed routing, with routability/timing feedback loops and a detailed router descended from TritonRoute.
DREAMPlace is one of the clearest SOTA signals for our placer because our placer is already PyTorch/Nesterov-like. The lesson is not just GPU use; it is a clean separation between differentiable global placement kernels, detailed placement, routability, and timing extensions.
Learning-based placement is relevant to us only after we have a robust conventional flow. Google Circuit Training frames placement as a learned sequential decision problem. TILOS and follow-on work emphasize reproducibility, stronger baselines, and full-flow evaluation.
Before detailed A*, the router builds coarse guide reservations, charges congestion history, and seeds guide candidates. Single-run benchmarks have varied between 0 / 7 and 0 / 12 unique opened nets; per-run variance is dominated by placer non-determinism (PyTorch CUDA without explicit seed), so individual scores should not be read as exact router quality.
Branch guides are no longer only fallback hints. Long or hard branches try guide-first routing, and the guide centerline becomes a soft multi-layer sketch corridor for detailed A*.
Detailed ECO can remove a target route, reroute it, recursively reroute blockers, and rollback the whole transaction if the result is worse.
Endpoint access is now required for correctness, not just an enhancement: with ROUTER_ENDPOINT_ACCESS=0 the current binary emits 199 shorts. The radial-access nodes are not a full pin-access oracle yet — they only add planar (LayerEdge) connectivity, not via edges, and they only check obstacles per-layer at the candidate point.
Rescue and patch candidates are pre-checked for trace-via, trace-pad, trace-trace, via-track, via-via, and via-pad conflicts before commit. Disabling it (KVM_RESCUE_GEOMETRY_VALIDATION=0) makes scores worse, confirming the validator is helping rather than rejecting good candidates.
Differential-pair N-side routing applies a soft reward for following the P-side path. Confirmed empirically that DIFF_PAIR_COUPLING_STRENGTH 0.15 vs 0.35 produces byte-identical router output on this board, and the bias is too small to flip A* path selection given current congestion costs. Treat this as infrastructure landed, not a closed gap. The real fix is true coupled co-search (see Next Gaps).
TOML constraints, Python board config, Rust router flags, KiCad DRC, and cleanup heuristics all carry part of the truth.
Commercial PCB flows use one constraint database that placement, routing, tuning, checking, and reporting all consult.
Promote constraints into a typed design graph with rule provenance on every placement, routing, and DRC decision.
Our placer is already in the analytical/Nesterov family, but routability feedback is still coarse and legalization is mostly greedy.
OpenROAD/DREAMPlace-style flows separate global placement, detailed placement, legalization, routability, and timing feedback.
Add global/detailed/legalize phases with congestion inflation, pin-access cost, board-edge mechanics, and benchmarked seeds.
Our router has 3D A*, BGA fanout, congestion negotiation, and emerging ECO patching, but detailed routing is still late and local.
SOTA routers use route guides, pin-access oracles, recursive shove, transactional edits, and rule-aware glossing as core stages.
Insert global routing before detailed routing, then make the detailed router guide-aware, shove-capable, and transactional.
We check with KiCad DRC and our own overlap/connectivity tools after generation, then feed some failure state into reruns.
Enterprise PCB flows bring SI, PI, thermal, DFM, mechanical, and rule checks earlier so they influence layout decisions.
Turn verification outputs into weighted maps and structured failure records that can drive placement and routing, not just report pass/fail.
We have repeatable scripts and fast loops, but benchmark datasets, fixed seeds, competitor harnesses, and per-commit quality dashboards are incomplete.
OpenROAD, DREAMPlace, and TILOS-style work make quality claims against shared suites and full-flow post-route metrics.
Track area, HPWL, wirelength, vias, shorts, opens, DRC, runtime, seed, and knobs for every benchmarked board.
Highest priority. Per-pad legal escape graph computed before routing: for each pad, enumerate access points (legal exit directions, layers, via sites that do not intersect adjacent pads). A* uses access points as graph endpoints, not the pad center. Fixes the J5 front-panel header failures (HDD_LED_N, PWR_LED_P, RST_BTN_L) where traces approach through GND-pad territory and get rejected, and the I2C tree failures where multi-drop branch points have no escape model.
The current pair coupling bias is decorative on this board (proven no-op). Replace with coupled 2-net A* where the search state is (P_node, N_node) and edges enforce pair gap + skew, OR plan the pair as a bundle: reserve a width = 2×trace + gap corridor on each chosen layer, then commit P and N together. Fixes the "other side took the only channel" failures (CSI_D1N, HDMID2P).
AVDD-style failures (AVDD12_FILT, AVDD33_FILT, PCKIN_FILT, REXT_PIN) are short 2-pin nets connecting a discrete passive to an IC pin near the BGA. Treat them as a dedicated phase before BGA escape: identify by topology, route with a local Steiner solver that knows plane/cutout geometry, reserve their corridor and via sites first.
Replace rectilinear MST with FLUTE/Hanan-grid Steiner tree builder, congestion-aware. Multi-drop buses (I2C_SCL, I2C_SDA reaching 3+ destinations) currently fail because branch-point selection ignores the congestion landscape. Smaller scope than the oracle but well-studied.
Move strict pre-commit validation + recursive shove into the normal sequential routing commit path, not just rescue/repair. Routes that would fail validation should retry with shove rather than commit-then-sweep-then-fail. Lower priority once the access oracle exists, since fewer sweeps will fire.
The foundation is credible: source-generated schematics, a typed design graph, an analytical placer, Rust routing, live logs, renders, and scripted validation. That is stronger reproducibility than many GUI-first flows.
Global capacity reservation, sketch-style guide intent, endpoint radial access, recursive ECO shove, and strict candidate validation are in the core flow. The remaining failures concentrate in four mechanisms — front-panel header pin access, coupled diff-pair channels, filter islands near the BGA, and I2C bus topology — each of which has a specific architectural fix on the Next Gaps list.
After a parameter sweep showed that the recent score regression was placer non-determinism rather than router quality, we read the per-net failure logs and found that the same eleven nets fail across every router configuration. They cluster into four mechanisms — front-panel header pin access, coupled diff-pair channels, filter islands near the BGA, and I2C bus topology — each mapping to a specific Next Gap on this page.
Read the war story