A placer and router that work from intent.
KV Boards turns structured circuit intent into placed, routed, DRC checked KiCad boards. The core is a Rust analytical placer paired with a 3D visibility router, with KiCad DRC used as the external truth source.
Not an autorouter bolted onto a CAD file.
The user gives electrical intent, board constraints, and component choices. The pipeline owns placement, routing, validation, and generated artifacts.
Placement and routing exchange pressure through congestion maps, failed-route weights, DRC hints, and generic repair passes.
The result is a real KiCad PCB plus render assets, not a screenshot of a theoretical route.
How the engine closes a board.
Typed DesignGraph
The board starts as structured TOML, not hand-edited KiCad state. Components, nets, stackup, edge constraints, placement hints, and routing constraints become one Rust data model.
Analytical placement
The placer treats component coordinates as a continuous optimization problem: smooth wirelength, density pressure, constraint springs, routability pressure, then legalization.
Plane-aware preparation
Power and ground access is planned before routing. Plane-backed pads get targeted access instead of burning signal-layer capacity on rails that should be handled by copper pours or internal planes.
3D visibility routing
The router builds a continuous-coordinate product graph across signal layers. A* searches real geometry; Pathfinder-style history makes crowded channels more expensive across iterations.
Transactional repair
Failed or DRC-reported sites become generic repair hints. Ripup, shove, direct bridge, ECO, and via validation all run with rollback instead of manual net-specific fixes.
DRC-backed output
The pipeline writes KiCad boards, runs KiCad DRC, exports SVG/PNG/GLB assets, and feeds structured results back into the next round.
Built for generated hardware, not manual babysitting.
Placement sees global congestion and prior-round failures, so it learns to open channels before the detailed router starts.
Pads, traces, vias, and keepouts stay in board units. The router is not fighting a coarse cell grid when clearances are tight.
F.Cu, inner signal layers, and B.Cu are modeled as one product graph with via edges and per-layer costs.
Escape reservations, microvia-sized sites, row-aware endpoint access, and diff-pair-aware fanout are first-class router stages.
KiCad reports become geometry hints: pad-to-pad, track endpoint, component patch, and exact short sites without hardcoded component or net names.
Zero-state runs produce isolated /tmp boards plus bench JSON, so claims can be tied to code, seed, and TOML input.
The next frontier is board-area pressure.
Now that the placer and router can close small generated boards, the next hard problem is shrinking the outline while preserving DRC. That should be another optimization loop, not a list of hand-picked component positions.